Testing and design verification Neither of these topics can be over-emphasised. If a fabricated device cannot be tested, it is worthless. However, 100% testing is virtually impossible with many modern VLSI designs, especially those containing significant amounts of RAM. A compromise must be reached in which the test strategy used shows that there is a good probability that the design is correct. Design for testability is virtually a subject in its own right, and is covered elsewhere. Verification of full custom designs is required to avoid the possibility that an error can be generated by the designer in translating from the desired schematic to layout form (though no design rule may have been broken). The risk (in terms of wasted time and fabrication costs) demands that efforts be made to establish that the schematic and the layout correspond to exactly equivalent circuits. Verification involves extracting (using an appropriate CAD tool) a netlist and a list of components ...
While the standard-cells-based design is often referred to as full custom design , it is less so in a strict sense because the cells are pre-designed for general use and the same cells are used in a variety of chip designs. In a more comprehensive custom design, the whole mask is created from scratch, without the use of any libraries.However, the expense of developing a design style like this is becoming prohibitively expensive. As a result, the idea of design reuse is gaining attention and becoming popular as a way to cut down on design cycle time and production costs. The design of a memory cell, whether static or dynamic, may be the most rigorous complete custom design.There will be no alternative to high density memory chip design , since the same layout design is repeated.Using a combination of different design types on the same chip, such as regular cells, data-path cells, and PLAs, can achieve a good compromise in logic chip design. Design productivity is normally ver...