Full Custom Design

While the standard-cells-based design is often referred to as full custom design , it is less so in a strict sense because the cells are pre-designed for general use and the same cells are used in a variety of chip designs. In a more comprehensive custom design, the whole mask is created from scratch, without the use of any libraries.However, the expense of developing a design style like this is becoming prohibitively expensive. As a result, the idea of design reuse is gaining attention and becoming popular as a way to cut down on design cycle time and production costs. The design of a memory cell, whether static or dynamic, may be the most rigorous complete custom design.There will be no alternative to high density memory chip design , since the same layout design is repeated.Using a combination of different design types on the same chip, such as regular cells, data-path cells, and PLAs, can achieve a good compromise in logic chip design. Design productivity is normally very poor in real full-custom layouts, where the designer must do the geometry, orientation, and positioning of each transistor individually, typically 10-20 transistors per day, per designer.

Due to the high labour cost, full-custom design is seldom used in digital CMOS VLSI. The production of high-volume products such as memory chips, high-performance microprocessors, and FPGA masters are exceptions to this rule.The Intel 486 microprocessor chip, which is a good example of a hybrid full-custom design, is shown in Figure 1. On a single chip, one can see four different design styles: Memory banks (RAM cache), bit-slice data-path modules, and regular cells and PLA blocks make up the majority of the control circuitry.

Figure-1 Mask layout of the Intel 486 microprocessor chip, as an example of full-custom design.

SEMI CUSTOM DESIGN:

In this style of design , all most all the basic building block are used from the standard cells liabrary. Only few cells are designed from the begning, which are not available in this standard cell liabrary or to be optimized for a specific target. The approach is faster compare to full- custom style but slower than the standard cell base design. Performance -wise also, it is superior to the standard cell – based design but inferior to the full custom designed

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Concepts of Regularity, Modularity and Locality

By splitting the large structure into many sub-modules, the hierarchical design approach eliminates design complexity. To make the process easier, other design principles and approaches are usually needed. Regularity ensures that a large system's hierarchical decomposition can produce as many simple and identical blocks as possible.The design of array structures made up of similar cells, such as a parallel multiplication array, is a good example of regularity. Regularity can be seen at all levels of abstraction: uniformly sized transistors simplify the design at the transistor stage. Identical gate structures can be used at the logic level, and so on.A 2-1 MUX (multiplexer), a D-type edge-triggered flip flop, and a one-bit full adder are shown in Figure 7 as standard circuit-level designs. All of these circuits were created solely with inverters and tri-state buffers. This theory can be used to create a variety of different functions if the designer has a limited library of well-d...

Gate Array Design

The gate array (GA) comes after the FPGA because of the quick prototyping capability. As user programming is used to implement the design of the FPGA chip, metal mask design and processing is used to implement the design of the gate array. A two-step manufacturing process is needed for gate array implementation: The first phase, which uses generic (standard) masks, leaves each GA chip with an array of uncommitted transistors. These uncommitted chips can be saved for later customization after the metal interconnects between the array's transistors are defined (Fig. 1). Since the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-around time can be still short, a few days to a few weeks. Figure 2 depicts a gate array chip's corner, which includes bonding pads on the left and bottom sides, diodes for I/O protection, nMOS and pMOS transistors for chip output driver circuits in the neighbouring areas of bonding pads, arrays of nMOS and pMOS tra...

Comparison Among Various Design Styles

Testing and design verification Neither of these topics can be over-emphasised. If a fabricated device cannot be tested, it is worthless. However, 100% testing is virtually impossible with many modern VLSI designs, especially those containing significant amounts of RAM. A compromise must be reached in which the test strategy used shows that there is a good probability that the design is correct. Design for testability is virtually a subject in its own right, and is covered elsewhere. Verification of full custom designs is required to avoid the possibility that an error can be generated by the designer in translating from the desired schematic to layout form (though no design rule may have been broken). The risk (in terms of wasted time and fabrication costs) demands that efforts be made to establish that the schematic and the layout correspond to exactly equivalent circuits. Verification involves extracting (using an appropriate CAD tool) a netlist and a list of components ...

VLSI DESIGN STYLES

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