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Comparison Among Various Design Styles

  Testing and design verification

Neither of these topics can be over-emphasised. If a fabricated device cannot be tested, it is worthless. However, 100% testing is virtually impossible with many modern VLSI designs, especially those containing significant amounts of RAM. A compromise must be reached in which the test strategy used shows that there is a good probability that the design is correct. Design for testability is virtually a subject in its own right, and is covered elsewhere.

Verification of full custom designs is required to avoid the possibility that an error can be generated by the designer in translating from the desired schematic to layout form (though no design rule may have been broken).

The risk (in terms of wasted time and fabrication costs) demands that efforts be made to establish that the schematic and the layout correspond to exactly equivalent circuits.

Verification involves extracting (using an appropriate CAD tool) a netlist and a list of components (both intentional and parasitic) from the physical layout. The netlist can then be compared with the original schematic.

Connectivity checkers are available to check for open-circuits or shorts in the power distribution system, or for inadvertent shorting of gate outputs.

Extractors are capable of determining information about the components present in a physical design (for example, capacitance and resitance values, transistor dimensions, and occasionally inductance values). These may often be compared with the schematic to check for errors.

Timing verification requires accurate models of the circuit elements and a suitable means for precise definition of rise and fall times. This is reasonably practical where the number of active devices is not too great by use of circuit simulators. Where thousands of gates are present, such simulators cannot be used, and logic simulators with simpler and less accurate device models must be used.

Comparison Among Various Design Styles



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