Skip to main content

Field Programmable Gate Array (FPGA)

 For chip implementation of specified algorithms or logic functions, a variety of design styles can be considered. Each design style has its own advantages and disadvantages, so designers must make an informed decision in order to provide functionality at a low cost.

Field Programmable Gate Array (FPGA)

Users may order fully fabricated FPGA chips with thousands of logic gates or even more, as well as programmable interconnects, for custom hardware programming to achieve desired functionality. This design style allows for fast prototyping as well as cost-effective chip design, which is particularly useful for low-volume applications. I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures make up a typical field programmable gate array (FPGA) chip. Programming of RAM cells whose output terminals are attached to the gates of MOS pass transistors is used to programme the interconnects.Figure 1 depicts the general architecture of an XILINX FPGA. Figure 2 shows a more detailed view of the locations of switch matrices used for interconnect routing.

Figure 3 depicts a basic CLB (model XC2000 from XILINX). Four signal input terminals (A, B, C, and D), a clock signal terminal, user-programmable multiplexers, an SR-latch, and a look-up table make up the system (LUT). The LUT is a digital memory that stores the Boolean function's truth table. As a result, it can produce any four-variable function or any two-variable function. The control terminals of multiplexers are not shown explicitly in Fig.3.

The CLB is set up in such a way that its array can be programmed to perform a variety of logic functions. To map complex functions, more sophisticated CLBs have been added. An FPGA chip's typical design flow begins with a behavioural summary of its features written in a hardware description language like VHDL.The synthesised architecture is then divided into circuits or logic cells using technology mapping (or partitioning). The chip design is fully defined in terms of available logic cells at this stage. Following that, the placement and routing stage assigns individual logic cells to FPGA sites (CLBs) and establishes cell routing patterns based on the netlist.

                                                Figure-1: General architecture of Xilinx FPGAs


                   Figure-2: Detailed view of switch matrices and interconnection routing between CLBs.
Figure-3: XC2000 CLB of the Xilinx FPGA.

After routing is complete, the design's on-chip performance can be simulated and tested before the design is downloaded for FPGA programming. The chip's programming is true for as long as it is turned on, or until new programming is completed. In most cases, maximum utilisation of the FPGA chip region is not possible; as a result, several cell sites can go unutilized.

The most significant benefit of FPGA-based design is the extremely short time taken from the start of the design process to the availability of a working chip. Since the FPGA chip does not need any physical manufacturing, a functional sample can be obtained almost as soon as the concept is mapped into a specific technology. FPGA chips are typically more higher than other realisation options (such as gate array or standard cells) for the same design, but they are a very useful choice for small-volume ASIC chip development and quick prototyping, FPGA offers a very valuable option.







Comments

Post a Comment

Popular posts from this blog

Concepts of Regularity, Modularity and Locality

 By splitting the large structure into many sub-modules, the hierarchical design approach eliminates design complexity. To make the process easier, other design principles and approaches are usually needed. Regularity ensures that a large system's hierarchical decomposition can produce as many simple and identical blocks as possible.The design of array structures made up of similar cells, such as a parallel multiplication array, is a good example of regularity. Regularity can be seen at all levels of abstraction: uniformly sized transistors simplify the design at the transistor stage. Identical gate structures can be used at the logic level, and so on.A 2-1 MUX (multiplexer), a D-type edge-triggered flip flop, and a one-bit full adder are shown in Figure 7 as standard circuit-level designs. All of these circuits were created solely with inverters and tri-state buffers. This theory can be used to create a variety of different functions if the designer has a limited library of well-d...
Post a Comment
Read more

Gate Array Design

The gate array (GA) comes after the FPGA because of the quick prototyping capability. As user programming is used to implement the design of the FPGA chip, metal mask design and processing is used to implement the design of the gate array. A two-step manufacturing process is needed for gate array implementation: The first phase, which uses generic (standard) masks, leaves each GA chip with an array of uncommitted transistors. These uncommitted chips can be saved for later customization after the metal interconnects between the array's transistors are defined (Fig. 1). Since the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-around time can be still short, a few days to a few weeks. Figure 2 depicts a gate array chip's corner, which includes bonding pads on the left and bottom sides, diodes for I/O protection, nMOS and pMOS transistors for chip output driver circuits in the neighbouring areas of bonding pads, arrays of nMOS and pMOS tra...
Post a Comment
Read more

Design Hierarchy

  Design Hierarchy The hierarchy, or 'divide and conquer' strategy, entails breaking down a subsystem into sub-modules and then repeating the process on the sub-modules until the smaller parts' complexity is manageable. This method is similar to how large programmes are broken down into smaller and smaller parts before simple subroutines with well-defined functions and interfaces can be written in software. The architecture of a VLSI chip can be expressed in three domains, as we've seen.As a result, each domain's hierarchy structure can be represented separately. However, it is important for design simplicity that the hierarchies in different domains can be easily mapped into one another. Figure 1 demonstrates the structural decomposition of a CMOS four-bit adder into its components as an example of structural hierarchy. Decomposing the adder into one-bit adders, separate carry and sum circuits, and finally individual logic gates is possible.The design of a simple c...
Post a Comment
Read more